704 search results - page 31 / 141 » On-chip logic minimization |
CORR
2007
Springer
14 years 9 months ago
2007
Springer
The Semantic Web drives towards the use of the Web for interacting with logically interconnected data. Through knowledge models such as Resource Description Framework (RDF), the S...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
ENTCS
2002
14 years 9 months ago
2002
We compare Meyer and Routley's minimal relevant logic B+ with the recent semanticsbased approach to subtyping introduced by Frisch, Castagna and Benzaken in the definition of...