704 search results - page 32 / 141 » On-chip logic minimization |
INFOCOM
2009
IEEE
15 years 4 months ago
2009
IEEE
—Packet classification is a function increasingly used in a number of networking appliances and applications. Typically, sists of a set of abstract classifications, and a set o...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
FPGA
2007
ACM
15 years 4 months ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
FCCM
2007
IEEE
15 years 4 months ago
2007
IEEE
FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...