704 search results - page 37 / 141 » On-chip logic minimization |
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a technique for memory optimization for a class of computations that arises in the field of correlated electronic structure methods such as coupled cluster and...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
DLOG
2009
14 years 7 months ago
2009
In this work we summarize our recent results on extending Description Logics for reasoning about prototypical properties and inheritance with exceptions. First, we focus our attent...
ISMVL
2003
IEEE
15 years 3 months ago
2003
IEEE
In earlier work [9], we defined CTL model-checking over finite-valued logics with De Morgan negation. In this paper, we extend this work to logics with intuitionistic, Galois an...
IJCAI
2003
14 years 11 months ago
2003
Current Description Logic reasoning systems provide only limited support for debugging logically erroneous knowledge bases. In this paper we propose new non-standard reasoning ser...