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» On-chip logic minimization
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FPGA
2008
ACM
155views FPGA» more  FPGA 2008»
14 years 11 months ago
A novel FPGA logic block for improved arithmetic performance
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
NPL
1998
129views more  NPL 1998»
14 years 9 months ago
Extraction of Logical Rules from Neural Networks
A new architecture and method for feature selection and extraction of logical rules from neural networks trained with backpropagation algorithm is presented. The network consists ...
Wlodzislaw Duch, Rafal Adamczak, Krzysztof Grabcze...
LPNMR
2009
Springer
15 years 4 months ago
A Default Approach to Semantics of Logic Programs with Constraint Atoms
We define the semantics of logic programs with (abstract) constraint atoms in a way closely tied to default logic. Like default logic, formulas in rules are evaluated using the cl...
Yi-Dong Shen, Jia-Huai You
ADC
2003
Springer
128views Database» more  ADC 2003»
15 years 3 months ago
An algorithm for the induction of defeasible logic theories from databases
Defeasible logic is a non-monotonic logic with applications in rule-based domains such as law. To ease the development and improve the accuracy of expert systems based on defeasib...
Benjamin Johnston, Guido Governatori
MST
2010
122views more  MST 2010»
14 years 4 months ago
Self-Referential Justifications in Epistemic Logic
This paper is devoted to the study of self-referential proofs and/or justifications, i.e., valid proofs that prove statements about these same proofs. The goal is to investigate wh...
Roman Kuznets