704 search results - page 42 / 141 » On-chip logic minimization |
122
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CORR
2011
Springer
14 years 1 months ago
2011
Springer
Contemporary use of the term ’intension’ derives from the traditional logical Frege-Russell’s doctrine that an idea (logic formula) has both an extension and an intension. Al...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...
LPAR
2007
Springer
15 years 4 months ago
2007
Springer
In this paper we propose a nonmonotonic extension ALC + Tmin of the Description Logic ALC for reasoning about prototypical properties and inheritance with exception. The logic ALC ...
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
102
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ITC
1994
IEEE
15 years 1 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...