704 search results - page 45 / 141 » On-chip logic minimization |
DAWAK
2000
Springer
15 years 2 months ago
2000
Springer
In the context of multidimensional databases implemented on relational DBMSs through star schemes, the most effective technique to enhance performances consists of materializing re...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
CSL
2005
Springer
15 years 3 months ago
2005
Springer
Recent work establishes a direct link between the complexity of a linear logic proof in terms of the exchange rule and the topological complexity of its corresponding proof net, ex...
149
click to vote
WRLA
2010
14 years 8 months ago
2010
Abstract. This paper presents the foundation, design, and implementation of the Linear Temporal Logic of Rewriting model checker as an extension of the Maude system. The Linear Tem...
ISCA
1999
IEEE
15 years 2 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...