704 search results - page 50 / 141 » On-chip logic minimization |
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
DDECS
2009
IEEE
15 years 4 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
ICS
2000
Tsinghua U.
15 years 1 months ago
2000
Tsinghua U.
One of the main concerns in today's processor design is the issue logic. Instruction-level parallelism is usually favored by an out-of-order issue mechanism where instruction...
CORR
2010
Springer
14 years 7 months ago
2010
Springer
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...