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» On-chip logic minimization
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ICCAD
2008
IEEE
117views Hardware» more  ICCAD 2008»
15 years 4 months ago
A novel sequential circuit optimization with clock gating logic
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang
ESOP
2004
Springer
15 years 3 months ago
Extracting a Data Flow Analyser in Constructive Logic
Abstract. We show how to formalise a constraint-based data flow analysis in the specification language of the Coq proof assistant. This involves defining a dependent type of lat...
David Cachera, Thomas P. Jensen, David Pichardie, ...
VLSID
1998
IEEE
105views VLSI» more  VLSID 1998»
15 years 2 months ago
Optimizing Logic Design Using Boolean Transforms
When a Boolean function is transformed by exclusiveOR with a suitably selected transform function, the new functzon is often synthesized wzth significantly reduced hardware. `I�...
Pramit Chavda, James Jacob, Vishwani D. Agrawal
ACL
1990
14 years 11 months ago
Automated Inversion of Logic Grammars for Generation
We describe a system of reversible grammar in which, given a logic-grammar specification of a natural language, two efficient PROLOGprograms are derived by an off-line compilation...
Tomek Strzalkowski, Ping Peng
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 3 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar