704 search results - page 61 / 141 » On-chip logic minimization |
TCAD
1998
14 years 9 months ago
1998
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
DAC
2005
ACM
15 years 11 months ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate...
ICCAD
1997
IEEE
15 years 2 months ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
ISCA
1997
IEEE
15 years 2 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...