704 search results - page 7 / 141 » On-chip logic minimization |
ESTIMEDIA
2006
Springer
15 years 1 months ago
2006
Springer
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm ...
TC
2008
14 years 9 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
FCCM
2005
IEEE
15 years 3 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
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TVLSI
2008
14 years 9 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
EDCC
2008
Springer
14 years 11 months ago
2008
Springer
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...