Sciweavers

704 search results - page 81 / 141
» On-chip logic minimization
Sort
View
IFIP
2004
Springer
15 years 3 months ago
Prototyping Proof Carrying Code
Abstract We introduce a generic framework for proof carrying code, developed and mechanically verified in Isabelle/HOL. The framework defines and proves sound a verification con...
Martin Wildmoser, Tobias Nipkow, Gerwin Klein, Seb...
ISIPTA
2003
IEEE
15 years 3 months ago
Combining Belief Functions Issued from Dependent Sources
Dempster’s rule for combining two belief functions assumes the independence of the sources of information. If this assumption is questionable, I suggest to use the least speci...
Marco E. G. V. Cattaneo
ISVLSI
2002
IEEE
116views VLSI» more  ISVLSI 2002»
15 years 2 months ago
Multi-Output Timed Shannon Circuits
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
Mitchell A. Thornton, Rolf Drechsler, D. Michael M...
DAC
2007
ACM
15 years 11 months ago
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
KDD
2009
ACM
202views Data Mining» more  KDD 2009»
15 years 10 months ago
Correlated itemset mining in ROC space: a constraint programming approach
Correlated or discriminative pattern mining is concerned with finding the highest scoring patterns w.r.t. a correlation measure (such as information gain). By reinterpreting corre...
Siegfried Nijssen, Tias Guns, Luc De Raedt