704 search results - page 83 / 141 » On-chip logic minimization |
FPGA
2005
ACM
15 years 3 months ago
2005
ACM
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
PATMOS
2005
Springer
15 years 3 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
WECWIS
2002
IEEE
15 years 2 months ago
2002
IEEE
In the web context, it is difficult to disentangle presentation from process logic, and sometimes even data is not separate from the presentation. Consequently, it becomes to de...
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...
FPL
1999
Springer
15 years 2 months ago
1999
Springer
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...