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» On-chip logic minimization
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DAC
2009
ACM
15 years 11 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
ICFP
2002
ACM
15 years 9 months ago
A compiled implementation of strong reduction
Motivated by applications to proof assistants based on dependent types, we develop and prove correct a strong reducer and equivalence checker for the -calculus with products, sums...
Benjamin Grégoire, Xavier Leroy
DSN
2009
IEEE
15 years 4 months ago
Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor
Dynamic Information Flow Tracking (DIFT) is a promising security technique. With hardware support, DIFT prevents a wide range of attacks on vulnerable software with minimal perfor...
Hari Kannan, Michael Dalton, Christos Kozyrakis
INFOCOM
2007
IEEE
15 years 4 months ago
SmartTunnel: Achieving Reliability in the Internet
Abstract— Reliability is critical to a variety of network applications. Unfortunately, due to lack of QoS support across ISP boundaries, it is difficult to achieve even two 9s (...
Yi Li, Yin Zhang, Lili Qiu, Simon S. Lam
EPIA
2007
Springer
15 years 4 months ago
Towards Tractable Local Closed World Reasoning for the Semantic Web
Recently, the logics of minimal knowledge and negation as failure MKNF [12] was used to introduce hybrid MKNF knowledge bases [14], a powerful formalism for combining open and clos...
Matthias Knorr, José Júlio Alferes, ...