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» On-chip logic minimization
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RTSS
2008
IEEE
15 years 4 months ago
Synthesis of Optimal Interfaces for Hierarchical Scheduling with Resources
This paper presents algorithms that (1) facilitate systemindependent synthesis of timing-interfaces for subsystems and (2) system-level selection of interfaces to minimize CPU loa...
Insik Shin, Moris Behnam, Thomas Nolte, Mikael Nol...
FUZZIEEE
2007
IEEE
15 years 4 months ago
Tolerance-based and Fuzzy-Rough Feature Selection
— One of the main obstacles facing the application of computational intelligence technologies in pattern recognition (and indeed in many other tasks) is that of dataset dimension...
Richard Jensen, Qiang Shen
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
15 years 4 months ago
Optimization of regular expression pattern matching circuits on FPGA
Regular expressions are widely used in Network Intrusion Detection System (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to ...
Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang,...
ATS
2005
IEEE
91views Hardware» more  ATS 2005»
15 years 3 months ago
SOC Test Scheduling with Test Set Sharing and Broadcasting
11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ICLP
2004
Springer
15 years 3 months ago
On Programs with Linearly Ordered Multiple Preferences
The extended answer set semantics for logic programs allows for the defeat of rules to resolve contradictions. We propose a refinement of these semantics based on a preference rel...
Davy Van Nieuwenborgh, Stijn Heymans, Dirk Vermeir