895 search results - page 174 / 179 » On-line optimal timing control of switched systems |
107
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IEEEPACT
2009
IEEE
15 years 6 months ago
2009
IEEE
—Shared cache allocation policies play an important role in determining CMP performance. The simplest policy, LRU, allocates cache implicitly as a consequence of its replacement ...
118
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RSP
2007
IEEE
15 years 6 months ago
2007
IEEE
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis” (gap between silicon technology and actual SoC design capacity) and ...
117
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ICS
2007
Tsinghua U.
15 years 5 months ago
2007
Tsinghua U.
Process arrival pattern, which denotes the timing when different processes arrive at an MPI collective operation, can have a significant impact on the performance of the operatio...
MEMOCODE
2006
IEEE
15 years 5 months ago
2006
IEEE
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
CF
2004
ACM
15 years 5 months ago
2004
ACM
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...