As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
Despite of the fact that large line segment datasets are appearing more and more frequently in numerous applications involving spatial data, such as GIS 8, 9] multimedia 6] and ev...
A central issue in the design of modern communication networks is that of providing performance guarantees. This issue is particularly important if the networks support real-time t...
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatter...
We consider the problem of transforming a given sequential implementation of a data structure into a wait-free concurrent implementation. Given the code for different operations ...