Sciweavers

2542 search results - page 455 / 509
» One step ahead
Sort
View
CAV
1998
Springer
175views Hardware» more  CAV 1998»
15 years 3 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
CIKM
1998
Springer
15 years 3 months ago
Selectivity Estimation of Window Queries
Despite of the fact that large line segment datasets are appearing more and more frequently in numerous applications involving spatial data, such as GIS 8, 9] multimedia 6] and ev...
Guido Proietti, Christos Faloutsos
FOCS
1997
IEEE
15 years 3 months ago
General Dynamic Routing with Per-Packet Delay Guarantees of O(distance + 1 / session rate)
A central issue in the design of modern communication networks is that of providing performance guarantees. This issue is particularly important if the networks support real-time t...
Matthew Andrews, Antonio Fernández, Mor Har...
ICCAD
1996
IEEE
93views Hardware» more  ICCAD 1996»
15 years 3 months ago
VERILAT: verification using logic augmentation and transformations
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatter...
SPDP
1993
IEEE
15 years 3 months ago
How to Share an Object: A Fast Timing-Based Solution
We consider the problem of transforming a given sequential implementation of a data structure into a wait-free concurrent implementation. Given the code for different operations ...
Rajeev Alur, Gadi Taubenfeld