36 search results - page 4 / 8 » One-Level Cache Memory Design for Scalable SMT Architectures |
ISCA
2005
IEEE
13 years 12 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
IPPS
2009
IEEE
14 years 28 days ago
2009
IEEE
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
CLUSTER
2006
IEEE
14 years 10 days ago
2006
IEEE
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
IEEEPACT
2008
IEEE
14 years 21 days ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
ICC
2011
IEEE
12 years 5 months ago
2011
IEEE
Abstract—Content-Centric Networking is a new communication architecture that rethinks the Internet communication model, designed for point-to-point connections between hosts, and...