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ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
15 years 4 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
CCS
2003
ACM
15 years 2 months ago
Cryptographic tamper evidence
We propose a new notion of cryptographic tamper evidence. A tamper-evident signature scheme provides an additional procedure Div which detects tampering: given two signatures, Div...
Gene Itkis