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CIDR
2003
164views Algorithms» more  CIDR 2003»
14 years 11 months ago
Capacity Bound-free Web Warehouse
Web cache technologies have been developed as an extension of CPU cache, by modifying LRU (Least Recently Used) algorithms. Actually in web cache systems, we can use disks and ter...
Yahiko Kambayashi, Kai Cheng
ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
13 years 9 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
HPCA
2000
IEEE
15 years 2 months ago
Modified LRU Policies for Improving Second-Level Cache Behavior
Main memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches. With the trend of greater associativity in seco...
Wayne A. Wong, Jean-Loup Baer
DCC
2008
IEEE
14 years 12 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
SODA
2004
ACM
83views Algorithms» more  SODA 2004»
14 years 11 months ago
Caching queues in memory buffers
Motivated by the need for maintaining multiple, large queues of data in modern high-performance systems, we study the problem of caching queues in memory under the following simpl...
Rajeev Motwani, Dilys Thomas