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112
Voted
HPCA
2000
IEEE
15 years 4 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
104
Voted
ICPP
1999
IEEE
15 years 4 months ago
An Offline Algorithm for Dimension-Bound Analysis
The vector-clock size necessary to characterize causality in a distributed computation is bounded by the dimension of the partial order induced by that computation. In an arbitrar...
Paul A. S. Ward
110
Voted
IPPS
1999
IEEE
15 years 4 months ago
Non-Preemptive Scheduling of Real-Time Threads on Multi-Level-Context Architectures
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
Jan Jonsson, Henrik Lönn, Kang G. Shin
101
Voted
HIPC
1999
Springer
15 years 4 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
127
Voted
AAAI
2007
15 years 2 months ago
Hybrid Inference for Sensor Network Localization Using a Mobile Robot
In this paper, we consider a hybrid solution to the sensor network position inference problem, which combines a real-time filtering system with information from a more expensive,...
Dimitri Marinakis, David Meger, Ioannis M. Rekleit...