69 search results - page 11 / 14 » Online cache modeling for commodity multicore processors |
OOPSLA
2010
Springer
13 years 4 months ago
2010
Springer
Many language implementations, particularly for high-level and scripting languages, are based on carefully honed runtime systems that have an internally sequential execution model...
IPPS
2008
IEEE
14 years 27 days ago
2008
IEEE
The fact that graphics processors (GPUs) are today’s most powerful computational hardware for the dollar has motivated researchers to utilize the ubiquitous and powerful GPUs fo...
ESA
2001
Springer
13 years 11 months ago
2001
Springer
Suppose that a program makes a sequence of m accesses (references) to data blocks, the cache can hold k < m blocks, an access to a block in the cache incurs one time unit, and ...
IEEEPACT
2005
IEEE
14 years 2 days ago
2005
IEEE
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
SIGCOMM
2009
ACM
14 years 1 months ago
2009
ACM
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...