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ICCAD
2007
IEEE
140views Hardware» more  ICCAD 2007»
16 years 1 months ago
Thermal-aware Steiner routing for 3D stacked ICs
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
Mohit Pathak, Sung Kyu Lim
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
16 years 1 months ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
16 years 1 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
CVPR
2010
IEEE
16 years 21 days ago
Surface Stereo with Soft Segmentation
This paper proposes a new stereo model which encodes the simple assumption that the scene is composed of a few, smooth surfaces. A key feature of our model is the surfacebased rep...
Michael Bleyer, Carsten Rother, Pushmeet Kohli
CVPR
2010
IEEE
16 years 20 days ago
Tiered Scene Labeling with Dynamic Programming
Dynamic programming (DP) has been a useful tool for a variety of computer vision problems. However its application is usually limited to problems with a one dimensional or low tre...
Pedro Felzenszwalb, Olga Veksler