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ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 8 months ago
A timing analysis algorithm for circuits with level-sensitive latches
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
Jin-fuw Lee, Donald T. Tang, C. K. Wong
ERSA
2006
98views Hardware» more  ERSA 2006»
15 years 5 months ago
Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array
To date, some types of Optically Reconfigurable Gate Arrays (ORGAs) have been developed to realize capabilities of rapid reconfiguration with numerous reconfiguration contexts. How...
Minoru Watanabe, Fuminori Kobayashi
JCP
2008
120views more  JCP 2008»
15 years 4 months ago
High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis
This paper presents a high throughput VLSI architecture for Blackman windowing. Since most of the implementation of windowing functions for real time applications, are based on eit...
Kailash Chandra Ray, A. S. Dhar
ICCAD
2007
IEEE
88views Hardware» more  ICCAD 2007»
16 years 1 months ago
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Abstract—Because of the today’s market demand for highperformance, high-density portable hand-held applications, electronic system design technology has shifted the focus from ...
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa...
FPL
2003
Springer
114views Hardware» more  FPL 2003»
15 years 9 months ago
Power Analysis of FPGAs: How Practical is the Attack?
Recent developments in information technologies made the secure transmission of digital data a critical design point. Large data flows have to be exchanged securely and involve en...
François-Xavier Standaert, Loïc van Ol...