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DATE
2009
IEEE
90views Hardware» more  DATE 2009»
15 years 10 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...
PLDI
2006
ACM
15 years 9 months ago
Termination proofs for systems code
Program termination is central to the process of ensuring that systems code can always react. We describe a new program termination prover that performs a path-sensitive and conte...
Byron Cook, Andreas Podelski, Andrey Rybalchenko
116
Voted
CASSIS
2004
Springer
15 years 9 months ago
ESC/Java2: Uniting ESC/Java and JML
The ESC/Java tool was a lauded advance in effective static checking of realistic Java programs, but has become out-of-date with respect to Java and the Java Modeling Language (JML...
David R. Cok, Joseph Kiniry
CONCUR
2008
Springer
15 years 5 months ago
Distributed Timed Automata with Independently Evolving Clocks
Abstract. We propose a model of distributed timed systems where each component is a timed automaton with a set of local clocks that evolve at a rate independent of the clocks of th...
S. Akshay, Benedikt Bollig, Paul Gastin, Madhavan ...
ICDE
2011
IEEE
220views Database» more  ICDE 2011»
14 years 7 months ago
Generating test data for killing SQL mutants: A constraint-based approach
—Complex SQL queries are widely used today, but it is rather difficult to check if a complex query has been written correctly. Formal verification based on comparing a specifi...
Shetal Shah, S. Sudarshan, Suhas Kajbaje, Sandeep ...