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ASAP
2000
IEEE
102views Hardware» more  ASAP 2000»
13 years 10 months ago
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
DAC
2004
ACM
14 years 7 months ago
Heterogeneous MP-SoC: the solution to energy-efficient signal processing
To meet conflicting flexibility, performance and cost constraints of demanding signal processing applications, future designs in this domain will contain an increasing number of a...
Tim Kogel, Heinrich Meyr
DAC
2005
ACM
14 years 7 months ago
Fine-grained application source code profiling for ASIP design
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
Kingshuk Karuri, Mohammad Abdullah Al Faruque, Ste...
DAC
2002
ACM
14 years 7 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 4 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...