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» Opportunistic Transient-Fault Detection
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CSREAESA
2009
14 years 10 months ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
TON
2012
12 years 12 months ago
Opportunistic Flow-Level Latency Estimation Using Consistent NetFlow
—The inherent measurement support in routers (SNMP counters or NetFlow) is not sufficient to diagnose performance problems in IP networks, especially for flow-specific problem...
Myungjin Lee, Nick G. Duffield, Ramana Rao Kompell...
DFT
2007
IEEE
135views VLSI» more  DFT 2007»
15 years 3 months ago
Fault Secure Encoder and Decoder for Memory Applications
We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry....
Helia Naeimi, André DeHon
68
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SAFECOMP
2007
Springer
15 years 3 months ago
Experimental Evaluation of the DECOS Fault-Tolerant Communication Layer
This paper presents an experimental evaluation of the fault-tolerant communication (FTCOM) layer of the DECOS integrated architecture. The FTCOM layer implements different agreemen...
Jonny Vinter, Henrik Eriksson, Astrit Ademaj, Bern...
DSN
2006
IEEE
15 years 3 months ago
Automatic Instruction-Level Software-Only Recovery
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
Jonathan Chang, George A. Reis, David I. August