This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Using 802.11 concurrently for communications and positioning is problematic, especially if location-based services (e.g., indoor navigation) are concurrently executed with real-ti...
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
In the emerging high-speed packet-switched networks, fair packet scheduling algorithms in switches and routers will form an important component of the mechanisms that seek to sati...
: Ensemble Routing For Datacenter Networks Mike Schlansker, Yoshio Turner, Jean Tourrilhes, Alan Karp HP Laboratories HPL-2010-120 Networks, Ethernet, Multipath, Switching, Fault ...
Mike Schlansker, Yoshio Turner, Jean Tourrilhes, A...