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DAC
2001
ACM
16 years 2 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
MOBISYS
2008
ACM
16 years 1 months ago
Composcan: adaptive scanning for efficient concurrent communications and positioning with 802.11
Using 802.11 concurrently for communications and positioning is problematic, especially if location-based services (e.g., indoor navigation) are concurrently executed with real-ti...
Mikkel Baun Kjærgaard, Thomas King
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Optimal module and voltage assignment for low-power
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
Deming Chen, Jason Cong, Junjuan Xu
COMCOM
2004
110views more  COMCOM 2004»
15 years 1 months ago
On the latency and fairness characteristics of pre-order deficit round Robin
In the emerging high-speed packet-switched networks, fair packet scheduling algorithms in switches and routers will form an important component of the mechanisms that seek to sati...
Salil S. Kanhere, Harish Sethu
ANCS
2010
ACM
14 years 11 months ago
Ensemble routing for datacenter networks
: Ensemble Routing For Datacenter Networks Mike Schlansker, Yoshio Turner, Jean Tourrilhes, Alan Karp HP Laboratories HPL-2010-120 Networks, Ethernet, Multipath, Switching, Fault ...
Mike Schlansker, Yoshio Turner, Jean Tourrilhes, A...