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IPPS
2009
IEEE
15 years 4 months ago
Minimizing total busy time in parallel scheduling with application to optical networks
—We consider a scheduling problem in which a bounded number of jobs can be processed simultaneously by a single machine. The input is a set of n jobs J = {J1, . . . , Jn}. Each j...
Michele Flammini, Gianpiero Monaco, Luca Moscardel...
MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
14 years 9 months ago
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform ...
Florian Braun, John W. Lockwood, Marcel Waldvogel
MAM
2008
150views more  MAM 2008»
14 years 9 months ago
FPGA based string matching for network processing applications
String matching is a key problem in many network processing applications. Current implementations of this process using software are time consuming and cannot meet gigabit bandwid...
Janardhan Singaraju, John A. Chandy
ETFA
2006
IEEE
15 years 3 months ago
Low-Cost Optical Indoor Localization System for Mobile Objects without Image Processing
While being very successful in everyday life, GPSbased localization systems exhibit limited performance under trees, behind walls, and in closed rooms, and sometimes induce costs ...
Ralf Salomon, Matthias Schneider, Daniel Wehden
ERSA
2009
146views Hardware» more  ERSA 2009»
14 years 7 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...