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DATE
2004
IEEE
168views Hardware» more  DATE 2004»
15 years 1 months ago
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing
Energy efficient embedded systems consist of a heterogeneous collection of very specific building blocks, connected together by a complex network of many dedicated busses and inte...
Ingrid Verbauwhede, Patrick Schaumont, Christian P...
ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
15 years 6 months ago
Run-Time Execution of Reconfigurable Hardware in a Java Environment
We present tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware. We use JHDL to describe the ...
Laurie A. Smith King, Heather Quinn, Miriam Leeser...
73
Voted
INFOCOM
2009
IEEE
15 years 4 months ago
Topological Data Processing for Distributed Sensor Networks with Morse-Smale Decomposition
Abstract—We are interested in topological analysis and processing of the large-scale distributed data generated by sensor networks. Naturally a large-scale sensor network is depl...
Xianjin Zhu, Rik Sarkar, Jie Gao
83
Voted
FPGA
2000
ACM
120views FPGA» more  FPGA 2000»
15 years 1 months ago
A novel high throughput reconfigurable FPGA architecture
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...
Amit Singh, Luca Macchiarulo, Arindam Mukherjee, M...
MVA
1992
188views Computer Vision» more  MVA 1992»
14 years 10 months ago
The Programmable and Configurable Low Level Vision Unit of the HERMIA Machine
In this work the Low Level Vision Unit (LLVU) of the Heterogeneous and Reconfigurable Machine for Image Analysis (HERMIA) is described. The LLVU consists of the innovative integra...
Gaetano Gerardi, Giancarlo Parodi