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ICCD
2004
IEEE
158views Hardware» more  ICCD 2004»
15 years 6 months ago
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Z...
ISVLSI
2006
IEEE
104views VLSI» more  ISVLSI 2006»
15 years 3 months ago
Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning
We describe analog and mixed-signal primitives for implementing adaptive signal-processing algorithms in VLSI based on anti-Hebbian learning. Both on-chip calibration techniques a...
Miguel Figueroa, Esteban Matamala, Gonzalo Carvaja...
FPL
2009
Springer
105views Hardware» more  FPL 2009»
15 years 1 months ago
Run-time resource management in fault-tolerant network on reconfigurable chips
This paper investigates the challenges of run-time resource management in future coarse-grained network-onreconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature e...
Mohammad Hosseinabady, José L. Nú&nt...
IWSOC
2003
IEEE
117views Hardware» more  IWSOC 2003»
15 years 2 months ago
Design Considerations for Optically Connected Systems on Chip
This paper addresses some fundamental issues relating to the design of systems on chip that utilize optical interconnects. We present an information theoretical model for assessin...
Neal K. Bambha, Shuvra S. Bhattacharyya, Gary Euli...
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 9 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek