A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Z...
We describe analog and mixed-signal primitives for implementing adaptive signal-processing algorithms in VLSI based on anti-Hebbian learning. Both on-chip calibration techniques a...
Miguel Figueroa, Esteban Matamala, Gonzalo Carvaja...
This paper investigates the challenges of run-time resource management in future coarse-grained network-onreconfigurable-chips (NoRCs). Run-time reconfiguration is a key feature e...
This paper addresses some fundamental issues relating to the design of systems on chip that utilize optical interconnects. We present an information theoretical model for assessin...
Neal K. Bambha, Shuvra S. Bhattacharyya, Gary Euli...
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...