In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I...
Optimizations aimed at reducing the impact of memory operations on execution speed have long concentrated on improving cache performance. These efforts achieve a reasonable level...
In a M/M/N+M queue, when there are many customers waiting, it may be preferable to reject a new arrival rather than risk that arrival later abandoning without receiving service. O...
In this article we report on applications and extensions of weighted graph theory in the design and control of communication networks. We model the communication network as a weig...
Given two admission control algorithms that are cA-acceptcompetitive and cR-reject-competitive respectively, we give two ways to make an algorithm that is simultaneously O(cA)acce...