Software model checkers are being used mostly to discover specific types of errors in the code, since exhaustive verification of complex programs is not possible due to state explo...
We investigate resource allocation policies for time-division multiple access (TDMA) over fading channels in the power-limited regime. For frequency-flat block-fading channels and ...
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...