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RSP
2008
IEEE
182views Control Systems» more  RSP 2008»
15 years 8 months ago
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
RTSS
2007
IEEE
15 years 8 months ago
Adapting Futures: Scalability for Real-World Computing
Creating robust real-time embedded software is critical in combining the physical world with computing, such as in consumer electronics or robotics. One challenge is the complexit...
Johannes Helander, Risto Serg, Margus Veanes, Prit...
AGTIVE
2007
Springer
15 years 8 months ago
A First Experimental Evaluation of Search Plan Driven Graph Pattern Matching
Abstract. With graph pattern matching the field of graph transformation (GT) includes an NP-complete subtask. But for real-life applications it is essential that graph pattern mat...
Gernot Veit Batz, Moritz Kroll, Rubino Geiß
89
Voted
CC
2007
Springer
15 years 8 months ago
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung...
105
Voted
CC
2007
Springer
126views System Software» more  CC 2007»
15 years 8 months ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan
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