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CODES
2004
IEEE
15 years 5 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
128
Voted
CASES
2006
ACM
15 years 5 months ago
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
Won So, Alexander G. Dean
FPGA
2000
ACM
177views FPGA» more  FPGA 2000»
15 years 5 months ago
Automatic generation of FPGA routing architectures from high-level descriptions
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
Vaughn Betz, Jonathan Rose
ICS
2000
Tsinghua U.
15 years 5 months ago
Automatic loop transformations and parallelization for Java
From a software engineering perspective, the Java programming language provides an attractive platform for writing numerically intensive applications. A major drawback hampering i...
Pedro V. Artigas, Manish Gupta, Samuel P. Midkiff,...
VLDB
1995
ACM
97views Database» more  VLDB 1995»
15 years 5 months ago
Processing Object-Oriented Queries with Invertible Late Bound Functions
New demandsare put on query processing in Object-Oriented(00) databasesto provide efficient andrelationally completequery languages. A flexible 00 data model requires overloading ...
Staffan Flodin, Tore Risch
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