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GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 4 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
INFOCOM
2009
IEEE
15 years 5 months ago
Decentralized Stochastic Control of Delay Tolerant Networks
—We study in this paper optimal stochastic control issues in delay tolerant networks. We first derive the structure of optimal two-hop forwarding policies. In order to be implem...
Eitan Altman, Giovanni Neglia, Francesco De Pelleg...
ASPLOS
2010
ACM
15 years 4 months ago
Probabilistic job symbiosis modeling for SMT processor scheduling
Symbiotic job scheduling boosts simultaneous multithreading (SMT) processor performance by co-scheduling jobs that have ‘compatible’ demands on the processor’s shared resour...
Stijn Eyerman, Lieven Eeckhout
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CODES
2002
IEEE
15 years 4 months ago
The design context of concurrent computation systems
Design for performance-optimization of programmable, semicustom SoCs requires the ability to model and optimize the behavior of the system as a whole. Neither the hardware-testben...
JoAnn M. Paul, Christopher M. Eatedali, Donald E. ...
HYBRID
2000
Springer
15 years 2 months ago
Decidable Controller Synthesis for Classes of Linear Systems
A problem of great interest in the control of hybrid systems is the design of least restrictive controllers for reachability specifications. Controller design typically uses game t...
Omid Shakernia, Shankar Sastry, George J. Pappas