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DAC
2003
ACM
15 years 12 months ago
On-chip logic minimization
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
Roman L. Lysecky, Frank Vahid
KDD
2007
ACM
159views Data Mining» more  KDD 2007»
15 years 11 months ago
Practical guide to controlled experiments on the web: listen to your customers not to the hippo
The web provides an unprecedented opportunity to evaluate ideas quickly using controlled experiments, also called randomized experiments (single-factor or factorial designs), A/B ...
Ron Kohavi, Randal M. Henne, Dan Sommerfield
SMC
2007
IEEE
156views Control Systems» more  SMC 2007»
15 years 5 months ago
Dynamic fusion of classifiers for fault diagnosis
—This paper considers the problem of temporally fusing classifier outputs to improve the overall diagnostic classification accuracy in safety-critical systems. Here, we discuss d...
Satnam Singh, Kihoon Choi, Anuradha Kodali, Krishn...
93
Voted
EMSOFT
2006
Springer
15 years 2 months ago
New approach to architectural synthesis: incorporating QoS constraint
Embedded applications like video decoding, video streaming and those in the network domain, typically have a Quality of Service (QoS) requirement which needs to be met. Apart from...
Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
14 years 11 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri