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IPPS
2002
IEEE
15 years 11 months ago
A SIMD Vectorizing Compiler for Digital Signal Processing Algorithms
Short vector SIMD instructions on recent microprocessors, such as SSE on Pentium III and 4, speed up code but are a major challenge to software developers. We present a compiler t...
Franz Franchetti, Markus Püschel
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 11 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
MICRO
2002
IEEE
159views Hardware» more  MICRO 2002»
15 years 11 months ago
Master/slave speculative parallelization
Master/Slave Speculative Parallelization (MSSP) is an execution paradigm for improving the execution rate of sequential programs by parallelizing them speculatively for execution ...
Craig B. Zilles, Gurindar S. Sohi
SSIAI
2002
IEEE
15 years 11 months ago
Volumetric Segmentation via 3D Active Shape Models
A volumetric image segmentation algorithm has been developed and implemented by extending a 2D algorithm based on Active Shape Models. The new technique allows segmentation of 3D ...
Molly M. Dickens, Shaun S. Gleason, Hamed Sari-Sar...
DAC
2009
ACM
15 years 10 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers
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