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» Optimal Supply and Threshold Scaling for Subthreshold CMOS C...
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VLSID
2007
IEEE
209views VLSI» more  VLSID 2007»
15 years 9 months ago
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
Saraju P. Mohanty, Elias Kougianos
ISQED
2006
IEEE
176views Hardware» more  ISQED 2006»
15 years 3 months ago
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
Zhiyu Liu, Volkan Kursun
ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
15 years 2 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Analysis and optimization of gate leakage current of power gating circuits
— Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling dow...
Hyung-Ock Kim, Youngsoo Shin
DAC
2005
ACM
15 years 10 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...