166 search results - page 11 / 34 » Optimal System-on-Chip Test Scheduling |
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ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
VLSID
2002
IEEE
15 years 9 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
RTCSA
1999
IEEE
15 years 1 months ago
1999
IEEE
A non-blocking protocol that allows real-time tasks to share data in a multiprocessor system is presented in this paper. The protocol gives the means to concurrent real-time tasks...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
80
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EOR
2010
14 years 6 months ago
2010
: We describe a method to find low cost shift schedules with a time-varying service level that is always above a specified minimum. Most previous approaches used a two-step procedu...