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» Optimal System-on-Chip Test Scheduling
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DATE
2006
IEEE
142views Hardware» more  DATE 2006»
15 years 3 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
MANSCI
2008
128views more  MANSCI 2008»
14 years 9 months ago
Optimizing Call Center Staffing Using Simulation and Analytic Center Cutting-Plane Methods
We consider the problem of minimizing staffing costs in an inbound call center, while maintaining an acceptable level of service in multiple time periods. The problem is complicat...
Júlíus Atlason, Marina A. Epelman, S...
DAC
2012
ACM
12 years 12 months ago
Towards fault-tolerant embedded systems with imperfect fault detection
Many state-of-the-art approaches on fault-tolerant system design make the simplifying assumption that all faults are detected within a certain time interval. However, based on a d...
Jia Huang, Kai Huang, Andreas Raabe, Christian Buc...
DAGSTUHL
2008
14 years 11 months ago
Uniprocessor EDF Feasibility is an Integer Problem
The research on real-time scheduling has mostly focused on the development of algorithms that allows to test whether the constraints imposed on the task execution (often expressed ...
Enrico Bini
109
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CASES
2011
ACM
13 years 9 months ago
Cost-effective safety and fault localization using distributed temporal redundancy
Cost pressure is driving vendors of safety-critical systems to integrate previously distributed systems. One natural approach we have previous introduced is On-Demand Redundancy (...
Brett H. Meyer, Benton H. Calhoun, John Lach, Kevi...