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TVLSI
2010
13 years 29 days ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
13 years 12 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
DAC
1995
ACM
13 years 9 months ago
Register Allocation and Binding for Low Power
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
Jui-Ming Chang, Massoud Pedram
INFOCOM
2010
IEEE
13 years 4 months ago
Joint Random Access and Power Selection for Maximal Throughput in Wireless Networks
—In wireless networks, how to select transmit power that maximizes throughput is a challenging problem. On one hand, transmissions at a high power level could increase interferen...
Yan Gao, Zheng Zeng, P. R. Kumar
DAC
2007
ACM
14 years 7 months ago
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
Behnam Amelifard, Massoud Pedram