60 search results - page 7 / 12 » Optimal WCET-aware code selection for scratchpad memory |
98
Voted
ICASSP
2011
IEEE
14 years 3 months ago
2011
IEEE
To address the increasing demand for higher resolution and frame rates, processing speed (i.e. performance) and area cost need to be considered in the development of next generati...
120
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IEEEPACT
2009
IEEE
14 years 9 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
70
Voted
CORR
2006
Springer
14 years 11 months ago
2006
Springer
This paper presents a new functionality of the Automatic Differentiation (AD) Tool tapenade. tapenade generates adjoint codes which are widely used for optimization or inverse prob...
108
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IPPS
2005
IEEE
15 years 5 months ago
2005
IEEE
Abstract— We developed an automated environment to measure the memory access behavior of applications on high performance clusters. Code optimization for processor caches is cruc...
120
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CODES
2006
IEEE
15 years 5 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...