60 search results - page 9 / 12 » Optimal WCET-aware code selection for scratchpad memory |
IRI
2009
IEEE
15 years 4 months ago
2009
IEEE
A 4KB page size has been used for Virtual Memory since the sixties. In fact, today, the most common page size is still 4KB. Choosing a page size is finding the middle ground betwe...
81
Voted
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardwa...
80
Voted
ICS
2009
Tsinghua U.
15 years 4 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
HIPEAC
2007
Springer
15 years 3 months ago
2007
Springer
The XScale processor family provides user-controllable independent configuration of CPU, bus, and memory frequencies. This feature introduces another handle for the code optimizat...
85
Voted
ASPDAC
1998
ACM
15 years 1 months ago
1998
ACM
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...