5 search results - page 1 / 1 » Optimal cell flipping in placement and floorplanning |
DAC
2006
ACM
15 years 10 months ago
2006
ACM
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
FPGA
1998
ACM
15 years 1 months ago
1998
ACM
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
TVLSI
2010
14 years 4 months ago
2010
The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
Dramatic progress has been made in algorithms for placement and routing over the last 5 years, with improvements in both speed and quality. Combining placement and routing into a ...