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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 9 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
MOBICOM
2012
ACM
13 years 20 hour ago
MIDU: enabling MIMO full duplex
Given that full duplex (FD) and MIMO both employ multiple antenna resources, an important question that arises is how to make the choice between MIMO and FD? We show that optimal ...
Ehsan Aryafar, Mohammad Ali Khojastepour, Karthike...
INFOCOM
2008
IEEE
15 years 4 months ago
MPLOT: A Transport Protocol Exploiting Multipath Diversity Using Erasure Codes
—In this paper, we propose a novel transport protocol that effectively utilizes available bandwidth and diversity gains provided by heterogeneous, highly lossy paths. Our Multi-P...
Vicky Sharma, Shivkumar Kalyanaraman, Koushik Kar,...
NOMS
2008
IEEE
15 years 4 months ago
Host-aware routing in multicast overlay backbone
— To support large-scale Internet-based broadcast of live streaming video efficiently in content delivery networks (CDNs), it is essential to implement a cost-effective overlay ...
Jun Guo, Sanjay Jha
ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
15 years 1 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...