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» Optimal hierarchical energy efficient design for MANETs
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DAC
2000
ACM
15 years 10 months ago
Function-level power estimation methodology for microprocessors
We have developed a function-level power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build th...
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag ...
ICCCN
2007
IEEE
15 years 1 months ago
Localized and Configurable Topology Control in Lossy Wireless Sensor Networks
Wireless sensor networks (WSNs) introduce new challenges to topology control due to the prevalence of lossy links. We propose a new topology control formulation for lossy WSNs that...
Guoliang Xing, Chenyang Lu, Robert Pless
MOBIHOC
2007
ACM
15 years 9 months ago
Cross-layer latency minimization in wireless networks with SINR constraints
Recently, there has been substantial interest in the design of crosslayer protocols for wireless networks. These protocols optimize certain performance metric(s) of interest (e.g....
Deepti Chafekar, V. S. Anil Kumar, Madhav V. Marat...
TC
2010
14 years 7 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
14 years 9 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...