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» Optimal integrated code generation for VLIW architectures
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PLDI
1995
ACM
15 years 1 months ago
Storage Assignment to Decrease Code Size
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, ge...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...
87
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EGH
2005
Springer
15 years 3 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 1 months ago
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 1 months ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain
KBSE
2010
IEEE
14 years 7 months ago
VikiBuilder: end-user specification and generation of visual wikis
With the need to make sense out of large and constantly growing information spaces, tools to support information management are becoming increasingly valuable. In prior work we pr...
Christian Hirsch, John G. Hosking, John C. Grundy