64 search results - page 11 / 13 » Optimal register assignment to loops for embedded code gener... |
CF
2009
ACM
15 years 5 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
114
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ASPLOS
2008
ACM
15 years 28 days ago
2008
ACM
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
86
Voted
CODES
2004
IEEE
15 years 2 months ago
2004
IEEE
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
106
Voted
LCTRTS
2005
Springer
15 years 4 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
109
Voted
LCTRTS
2005
Springer
15 years 4 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...