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DATE
2007
IEEE
109views Hardware» more  DATE 2007»
15 years 7 months ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
ATS
2003
IEEE
93views Hardware» more  ATS 2003»
15 years 6 months ago
Optimal System-on-Chip Test Scheduling
1 In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an exi...
Erik Larsson, Hideo Fujiwara
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
15 years 6 months ago
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique
In this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints. The multigrid-based technique is applied to...
Kai Wang, Malgorzata Marek-Sadowska
ICC
2007
IEEE
166views Communications» more  ICC 2007»
15 years 7 months ago
Dynamic Optimization of Secure Mobile Sensor Networks: A Genetic Algorithm
— We propose a reduced-complexity genetic algorithm for secure and dynamic deployment of resource constrained multi-hop mobile sensor networks. Mobility and security are relative...
Rahul Khanna, Huaping Liu, Hsiao-Hwa Chen
ICICIC
2006
IEEE
15 years 7 months ago
An Ant Colony Optimization Algorithm for Multiple Travelling Salesman Problem
Multiple travelling salesman problem (MTSP) is a typical computationally complex combinatorial optimization problem,which is an extension of the famous travelling salesman problem...
Pan Junjie, Wang Dingwei