Sciweavers

1768 search results - page 174 / 354
» Optimal routing in Chord
Sort
View
DCOSS
2005
Springer
15 years 7 months ago
Multi-query Optimization for Sensor Networks
The widespread dissemination of small-scale sensor nodes has sparked interest in a powerful new database abstraction for sensor networks: Clients “program” the sensors through ...
Niki Trigoni, Yong Yao, Alan J. Demers, Johannes G...
DAC
1997
ACM
15 years 5 months ago
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
Avaneendra Gupta, John P. Hayes
CODES
2004
IEEE
15 years 5 months ago
Power-aware communication optimization for networks-on-chips with voltage scalable links
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the ener...
Dongkun Shin, Jihong Kim
NETWORKING
2007
15 years 2 months ago
Optimization Models for the Radio Planning of Wireless Mesh Networks
In this paper we propose novel optimization models for the planning of Wireless Mesh Networks whose objective is to minimize the network installation cost, while providing full cov...
Edoardo Amaldi, Antonio Capone, Matteo Cesana, Fed...
109
Voted
ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
14 years 11 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...